Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory or SRAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) transistor (e.g., a p-type MOS (“PMOS”) transistor) paired with a second-conductivity-type MOS transistor (e.g., an n-type MOS (“NMOS”) transistor). CMOS cells can hold a logic state while drawing only very small amounts of current.
It is generally desirable that MOS transistors, whether used in a CMOS cell or used individually, provide good conductivity between the source and the drain of the MOS transistor when operating voltage is applied to the gate of the MOS transistor. In other words, it is desirable that current flows through the channel between the source and the drain when the MOS transistor is turned on.
The amount of current flowing through the channel of an MOS transistor is proportional to the mobility of charge carriers in the channel. Increasing the mobility of the charge carriers increases the amount of current that flows at a given gate voltage. Higher current flow through the channel allows the MOS transistor to operate faster. One of the ways to increase carrier mobility in the channel of a MOS transistor is to produce strain in the channel.
There are several ways to create strain in the channel region. One approach is to form stressed materials, such as epitaxially grown SiGe, in the source and drain regions of a MOS transistor. Unfortunately, this technique uses process steps that are not part of a conventional CMOS process flow, resulting in longer manufacturing times, higher yield losses due to removing the wafer from the CMOS process flow for epitaxy, and high cost. Additionally, these techniques are often used on only one type (e.g., P-type) of MOS field effect transistor (“FET”). Both P-type and N-type MOS FETs are found in a CMOS cell.
In some applications, two techniques are used to provide one type of stress in the PMOS portion of a CMOS cell (such as compressive SiGe epitaxy in the source/drain regions) and a second type of stress in the NMOS portion (such as by providing a tensile capping layer). This approach adds yet even more complexity to the CMOS fabrication process. In some cases, the tensile capping layer overlies the compressive SiGe epitaxy, reducing its effectiveness.
One technique uses compressive contact etch stop layers (“CESL”) in the PMOS portion of a CMOS cell, and a tensile CESL in the NMOS portion. FIG. 1 is a simplified cross section of a prior art CMOS cell 100 having an NMOS portion 102 and a PMOS portion 104 separated by isolation dielectric 106. A tensile CESL 108 overlies the NMOS portion 102, creating tensile strain in the channel region 110 beneath the gate 112. A compressive CESL 114 overlies the PMOS portion 104, creating compressive strain in the channel region 116 beneath the gate 118. Other details of the CMOS cell 100, such as gate/drain regions, are omitted for simplicity of illustration.
In order to achieve good electrical contacts in both the NMOS and PMOS portions of the CMOS cell 100, the contacts in both portions should open at the same time without damaging silicide. Two steps of contact etch would be very challenging because the contact barrier layer needs to be formed right after contact opening to form high quality contact. However, the tensile CESL 108 may etch very differently from the compressive CESL 114 in a contact etch process. The tight manufacturing tolerances of the contact etch process limit the types of materials and thicknesses of the two different CESLs, which limits the amount of strain produced by the CESLs.
It is desirable to provide a CMOS cell having enhanced mobility in both the PMOS and NMOS portions of the cell that avoids the disadvantages of the prior art.